ARM=yes
Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain’s power-on reset state machine.
Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET.
This register is Secure read/write only.
ARM | 0 (yes): Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) 23469 (no): Do not force the glitch detectors to be armed |